1. Field of the Invention
The present general inventive concept most directly relates to integrating test systems into electrical circuits. More specifically, the inventive concept relates to designing a test system to embed in an electrical circuit at circuit design time to prescribe the manner by which test response states are obtained by, and subsequently retrieved from scan registers, or “scan chains,” of the test system at test time. Scan chains are constructed so that test response states may be captured by the scan chains in a manner that corresponds to the test points of the electrical circuit, and may be retrieved from the scan chains in a manner independent from the manner by which the response states were captured to correspond to predetermined analysis requirements of the test system.
2. Description of the Related Art
Continuing advances in integrated circuit technology, coupled with steady progress in electronic circuit and circuit packaging design over the past several decades, has necessitated that considerable engineering resources be devoted to embedding test systems into primary circuitry. The concept of integrating test circuitry as part of the total circuit design follows what is generally referred to as the Design for Testing (DfT) paradigm. Advantageously, DfT techniques allow conducting quality control tests during one or more stages of the circuit manufacturing process, and even in the field, where previous techniques using, for example, traditional circuit probe systems cannot access the full set of desired circuit test points. Additionally, proper DfT techniques adhere to a doctrine that the test circuit be designed and constructed such that excessive impact on the form, fit and function of the primary circuit in which it resides is avoided.
One of the more common DfT techniques implements the so-called “boundary scan architecture,” which provides in-circuit hardware to serially input test data into a circuit-under-test (CUT), and to subsequently retrieve response data by serially shifting the data out of the CUT. Implementing the serial shifting of the test pattern data, as well as the response pattern data, requires some additional hardware, but allows data exchange between the CUT and, for example, automatic test equipment (ATE), without a large number of additional pins needed on the circuit package. The Institute of Electrical and Electronics Engineers (IEEE) Joint Test Action Group (JTAG) standard 1149.1, “Standard Test Access Port and Boundary Scan Architecture,” is a ubiquitous implementation of such serial scan testing.
In FIG. 1, there is illustrated a typical circuit configuration 110 implementing a boundary scan register 150. The boundary scan register 150 is formed from a plurality of state retention cells, representatively illustrated by state retention cells 125, 127, 128, and 129, serially interconnected, or “stitched”, into one or more “scan chains” 152. Typically, each state retention cell 125, 127, 128, 129 is situated between the application logic 120a-120d, such as in the circuit packages 115a-115b, and input and output ports thereof, such as package pins, representatively illustrated by package pin 126. The scan chain 152 is defined by the state retention cells, such as state retention cells 125, 127, 128, 129, interconnected from a test data in (TDI) terminal 154 to a test data out (TDO) terminal 155. Test pattern data and the corresponding response data are respectively entered into and retrieved from the scan chain 152 by serial shifting. Typically, the test pattern is serially entered into the scan chain 152 via the TDI terminal 154, corresponding response states are then captured at receiving state retention cells 128 and 129, and finally the response data are serially transferred out of the circuit via the TDO terminal 155.
In early implementations of the IEEE standard 1149.1, the boundary scan test ascertained only whether the various circuit packages, e.g., packages 115a-115b, were interconnected properly. To do so, response states corresponding to various test patterns would be determined a priori according to a circuit model. During testing, a state “1” would be set in, for example, state retention cell 127 as part of the test pattern, and a corresponding response state would be captured by state retention cells 128 and 129, which would be compared with modeled response states, i.e., “1,” to determine whether the interconnecting circuit traces 140 and 142 were undamaged and conducting properly.
Extensions to the foregoing boundary scan design now provide mechanisms to test functional circuitry as well, such as logic. Such testing of circuitry has become essential as manufacturing and design technologies produce denser circuits having a very large number of gates in a very small area. Similar to the interconnection testing by boundary scan, the functional testing proceeds by shifting test pattern data into a scan register, capturing the results on the opposite side of the logic, and shifting the test response data out of the scan register to be analyzed against modeled response data.
Responsive to the increasing complexity of modern circuitry, and the corresponding increase in test time, test compression techniques have been developed that include multiple, shorter scan chains incorporated into the CUT, as opposed to a single scan chain in a full scan implementation. One such compression technique is illustrated in FIG. 2, where the CUT 210 has incorporated therein a plurality of scan chains 230-1 to 230-n. The scan chains 230-1 to 230-n are respectively coupled to bidirectional pins 220-1 to 220-n, where the test data are input as test pattern vectors and corresponding response signature data is output. The states captured in the scan chains 230-1 to 230-n are processed at a multiple-input signature register (MISR) 240, which accumulates scan chain data over several clock cycles to produce a response signature corresponding to an applied test pattern.
In certain cases, such as, for example, in complex logic circuits, not all response states are modeled for a set of test pattern vectors. When a response state is unknown at test time, referred to as an “X-state,” its value at test time is preferably ignored. However, in certain test systems, the response analysis system is such that the X-states cannot simply be ignored. For example, in test systems using an MISR, X-states can corrupt the response signature to the extent that no determination can be made as to whether the circuit is correctly interconnected and/or operational. Moreover, X-states are typically interspersed among response data that have been modeled, and thus processing the response data in the presence of X-states requires additional measures that consume valuable circuit area and/or increases the time to test completion.
As illustrated in FIG. 3, response data sequences 330-1 to 330-n contain data as serially shifted from respective scan chains in the illustrated “DATA OUT” direction. A response vector, as used herein, refers to a plurality of response bits captured by respective state retention elements in a corresponding capture cycle and shifted out of respective scan chains concurrently. Representative response vectors are illustrated at response vectors 310, 312, and 314. Each of the response vectors 310, 312, 314 eventually arrives during an evaluation cycle at a response analyzer (not illustrated) as an evaluation vector 320.
The data sequences 330-1 to 330-n may contain unknown response states, i.e., X-states, representatively illustrated at X-state 315, and the response analyzer must produce meaningful results in the presence of those X-states. In systems using an MISR, for example, the X-states must be processed prior to entering the MISR to avoid corrupting the analysis. For example, each evaluation vector 320 containing an X-state may be masked at the input of the response analyzer, and vectors not containing an X-state, such as would result from response vectors 312 and 314, are allowed unmasked entry into the response analyzer. However, as is illustrated in FIG. 3, such masking severely depletes the number of usable evaluations vectors 320 by which to form a response signal, such as a response signature provided by an MISR, since only evaluation vectors corresponding to response vectors 312 and 314 are without X-states therein.
Several techniques have been developed to implement X-tolerant test response compression. Generally, such techniques include the addition of hardware in the test circuit, thereby increasing the circuit area consumed by the test circuit that could otherwise be used for functional circuitry or to decrease the size of the overall circuit. In light of the shortcomings of the existing X-state handling techniques, the need has been recognized for embedding serially accessed registers in a circuit to be tested, such as in scan testing systems, to accommodate efficient X-state handling according to the implemented analysis technique without an excessive penalty incurred by additional circuitry and/or additional test time.